`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:02:14 08/20/2015
// Design Name:   DelayEnable
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/DelayEnableTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DelayEnable
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module DelayEnableTest;

	// Inputs
	reg clk;
	reg enable;

	// Outputs
	wire enable2;

	// Instantiate the Unit Under Test (UUT)
	DelayEnable uut (
		.clk(clk), 
		.enable(enable), 
		.enable2(enable2)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		enable = 0;

		// Wait 100 ns for global reset to finish
		#100;
      enable = 1;
		#2;
		enable = 0;
		

	end

always begin
	#1; clk = ~clk;
end 
 
endmodule

